Digital Electronics Questions with Answers Set-2

The chip select logic for a certain DRAM chip in a memory system design is shown below. Assume that the memory system has 16 address lines denoted by to. What is the range of addresses (in hexadecimal) of the memory system that can get enabled by the chip select (CS) signal?

1. Register-to-register arithmetic operations only
2. Fixed-length instruction format
3. Hardwired control unit

The n-bit fixed-point representation of an unsigned real number X uses f bits for the fraction part. Let i=n-f. The range of decimal values for X in this representation is

Consider Z= X - Y, where X, Y and Z are all in sign-magnitude form. X and Y are each represented in n bits. To avoid overflow, the representation of Z would require a minimum of:

Consider three registers R1, R2, and R3 that store numbers in IEEE-754 single precision floating point format. Assume that R1 and R2 contain the values (in hexadecimal notation) 0x42200000 and 0xC1200000, respectively.

Consider three 4-variable functions fi, f2, and f3, which are expressed in sum-of-minterms as

$f_{1} = \Sigma (0,2,5,8,14)$

$f_{2} = \Sigma (2,3,6,8,14,15)$

$f_{3} = \Sigma (2,7,11,14)$

For the following circuit with one AND gate and one XOR gate, the output function f can be expressed as:

where the position of the binary point is between $b_{3}$ and $b_{2}$. Assume $b_{7}$ is the most significant bit. Some of the decimal numbers listed below cannot be represented exactly in the above representation:

Assume that in a certain computer, the virtual addresses are 64 bits long and the physical addresses are 48 bits long. The memory is word addressible. The page size is 8 kB and the word size is 4 bytes. The Translation Look-aside Buffer (TLB) in the address translation path has 128 valid entries. At most how many distinct virtual addresses can be translated without any TLB miss?

A multiplexer is placed between a group of 32 registers and an accumulator to regulate data movement such that at any given point in time the content of only one register will move to the accumulator. The minimum number of select lines needed for the multiplexer is

If there are m input lines and n output lines for a decoder that is used to uniquely address a byte-addressable 1 KB RAM, then the minimum value of m+n is

Two numbers are chosen independently and uniformly at random from the set {1,2,..., 13}. The probability (rounded off to 3 decimal places) that their 4-bit (unsigned) binary representations have the same most significant bit is ______.

Consider the sequential circuit shown in the figure, where both flip-flops used are positive edge-triggered D flip-flops.

The number of states in the state transition diagram of this circuit that have a transition back to the same state on some value of “in” is ___.

What is the minimum number of 2-input NOR gates required to implement a 4-variable function expressed in sum-of-minterms form as $f = \Sigma (0,2,5,7,8,10,13,15)$  Assume that all the inputs and their complements are available?

A processor has 16 integer registers (R0, R1, .. , R15) and 64 floating point registers (F0, F1,… , F63). It uses a 2-byte instruction format. There are four categories of instructions: Type-1, Type-2, Type-3, and Type-4. Type-1 category consists of four instructions, each with 3 integer register operands (3Rs). Type-2 category consists of eight instructions, each with 2 floating point register operands (2Fs). Type-3 category consists of fourteen instructions, each with one integer register operand and one floating point register operand (1R+1F). Type-4 category consists of N instructions, each with a floating point register operand (1F).

The maximum value of N is